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Features
* Fast Read Access Time - 70 ns * 5-volt Only Reprogramming * Sector Program Operation
- Single Cycle Reprogram (Erase and Program) - 512 Sectors (128 Bytes/Sector) - Internal Address and Data Latches for 128 Bytes Internal Program Control and Timer Hardware and Software Data Protection Fast Sector Program Cycle Time - 10 ms DATA Polling for End of Program Detection Low Power Dissipation - 50 mA Active Current - 100 A CMOS Standby Current Typical Endurance > 10,000 Cycles Single 5V 10% Supply CMOS and TTL Compatible Inputs and Outputs Commercial and Industrial Temperature Ranges Green (Pb/Halide-free) Packaging Option
* * * * *
512K (64K x 8) 5-volt Only Flash Memory AT29C512
* * * * *
1. Description
The AT29C512 is a 5-volt only in-system Flash programmable and erasable read only memory (PEROM). Its 512K of memory is organized as 65,536 words by 8 bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power dissipation of just 275 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 100 A. The device endurance is such that any sector can typically be written to in excess of 10,000 times. To allow for simple in-system reprogrammability, the AT29C512 does not require high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT29C512 is performed on a sector basis; 128 bytes of data are loaded into the device and then simultaneously programmed. During a reprogram cycle, the address locations and 128 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7. Once the end of a program cycle has been detected, a new access for a read or program can begin.
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2. Pin Configurations
Pin Name A0 - A15 CE OE WE I/O0 - I/O7 NC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect
2.1
32-lead PLCC Top View
A12 A15 NC NC VCC WE NC
2.2
32-lead TSOP (Type 1) Top View
I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6
14 15 16 17 18 19 20
A7 A6 A5 A4 A3 A2 A1 A0 I/O0
5 6 7 8 9 10 11 12 13
4 3 2 1 32 31 30
29 28 27 26 25 24 23 22 21
A14 A13 A8 A9 A11 OE A10 CE I/O7
A11 A9 A8 A13 A14 NC WE VCC NC NC A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
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3. Block Diagram
4. Device Operation
4.1 Read
The AT29C512 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.
4.2
Byte Load
Byte loads are used to enter the 128 bytes of a sector to be programmed or the software codes for data protection. A byte load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE.
4.3
Program
The device is reprogrammed on a sector basis. If a byte of data within a sector is to be changed, data for the entire sector must be loaded into the device. Any byte that is not loaded during the programming of its sector will be indeterminate. Once the bytes of a sector are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte has been loaded into the device, successive bytes are entered in the same manner. Each new byte to be programmed must have its high-to-low transition on WE (or CE) within 150 s of the low-to-high transition of WE (or CE) of the preceding byte. If a high-to-low transition is not detected within 150 s of the last low-to-high transition, the load period will end and the internal programming period will start. A7 to A15 specify the sector address. The sector address must be valid during each high-to-low transition of WE (or CE). A0 to A6 specify the byte address within the sector. The bytes may be loaded in any order; sequential loading is not required. Once a programming operation has been initiated, and for the duration of tWC, a read operation will effectively be a polling operation.
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4.4
Software Data Protection
A software controlled data protection feature is available on the AT29C512. Once the software protection is enabled a software algorithm must be issued to the device before a program may be performed. The software protection feature may be enabled or disabled by the user; when shipped from Atmel, the software data protection feature is disabled. To enable the software data protection, a series of three program commands to specific addresses with specific data must be performed. After the software data protection is enabled the same three program commands must begin each program cycle in order for the programs to occur. All software program commands must obey the sector program timing specifications. Once set, the software data protection feature remains active unless its disable command is issued. Power transitions will not reset the software data protection feature; however, the software feature will guard against inadvertent program cycles during power transitions. Once set, software data protection will remain active unless the disable command sequence is issued. After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, a read operation will effectively be a polling operation. After the software data protection's 3-byte command code is given, a byte load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. The 128 bytes of data must be loaded into each sector by the same procedure as outlined in the program section under device operation.
4.5
Hardware Data Protection
Hardware features protect against inadvertent programs to the AT29C512 in the following ways: (a) VCC sense - if VCC is below 3.8V (typical), the program function is inhibited; (b) VCC power on delay - once VCC has reached the VCC sense level, the device will automatically time out 5 ms (typical) before programming; (c) Program inhibit - holding any one of OE low, CE high or WE high inhibits program cycles; and (d) Noise filter - pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.
4.6
Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. In addition, users may wish to use the software product identification mode to identify the part (i.e., using the device code), and have the system software use the appropriate sector size for program operations. In this manner, the user can have a common board design for 256K to 4megabit densities and, with each density's sector size in a memory map, have the system software apply the appropriate sector size. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes.
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4.7 DATA Polling
The AT29C512 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle.
4.8
Toggle Bit
In addition to DATA polling the AT29C512 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.
4.9
Optional Chip Erase Mode
The entire device can be erased by using a 6-byte software code. Please see Software Chip Erase application note for details.
5. Absolute Maximum Ratings*
Temperature Under Bias................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on OE with Respect to Ground ...................................-0.6V to +13.5V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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6. DC and AC Operating Range
AT29C512-70 Operating Temperature (Case) VCC Power Supply Note: Com. Ind. 0C - 70C -40C - 85C 5V 5% Not recommended for New Designs. AT29C512-90 0C - 70C -40C - 85C 5V 10% AT29C512-12 0C - 70C -40C - 85C 5V 10% AT29C512-15 0C - 70C -40C - 85C 5V 10%
7. Operating Modes
Mode Read Program
(2)
CE VIL VIL VIL VIH X X X
OE VIL VIH VIH X
(1)
WE VIH VIL VIL X VIH X X
Ai Ai Ai Ai X
I/O DOUT DIN
5V Chip Erase Standby/Write Inhibit Program Inhibit Program Inhibit Output Disable Product Identification Hardware
High Z
X VIL VIH
High Z
VIL
VIL
VIH
A1 - A15 = VIL, A9 = VH,(3) A0 = VIL A1-A15 = VIL, A9 = VH,(3) A0 = VIH A0 = VIL A0 = VIH
Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code(4)
Software(5) Notes: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. 3. VH = 12.0V 0.5V. 4. Manufacturer Code: 1F, Device Code: 5D. 5. See details under Software Product Identification Entry/Exit.
8. DC Characteristics
Symbol ILI ILO ISB1 ISB2 ICC VIL VIH VOL VOH1 VOH2 Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage CMOS IOL = 2.1 mA IOH = -400 A IOH = -100 A; VCC = 4.5V 2.4 4.2 2.0 0.45 Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCC - 0.3V to VCC CE = 2.0V to VCC f = 5 MHz; IOUT = 0 mA Com. Ind. Min Max 10 10 100 300 3 50 0.8 Units A A A A mA mA V V V V V
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9. AC Read Characteristics
AT29C512-70 Symbol tACC tCE
(1) (2)
AT29C512-90 Min Max 90 90 0 0 0 40 25
AT29C512-12 Min Max 120 120 0 0 0 50 30
AT29C512-15 Min Max 150 150 0 0 0 70 40 Units ns ns ns ns ns
Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first
Min
Max 70 70
tOE tDF
0 0 0
35 10
(3)(4)
tOH
Note:
Not recommended for New Designs.
10. AC Read Waveforms(1)(2)(3)(4)
Notes:
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested.
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11. Input Test Waveforms and Measurement Level
tR, tF < 5 ns
12. Output Test Load
70 ns
5.0V 1.8K OUTPUT PIN 1.3K 30pF 1.3K 1.8K OUTPUT PIN 100pF
90/120/150 ns
5.0V
13. Pin Capacitance
f = 1 MHz, T = 25C(1)
Symbol CIN COUT Note: Typ 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V
1. This parameter is characterized and is not 100% tested.
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14. AC Byte Load Characteristics
Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tWPH Parameter Address, OE Set-up Time Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data, OE Hold Time Write Pulse Width High Min 0 50 0 0 90 35 0 100 Max Units ns ns ns ns ns ns ns ns
15. AC Byte Load Waveforms
15.1 WE Controlled
OE tOES tOEH
ADDRESS tAS CE tCS WE tWPH tWP tAH tCH
tDS
DATA IN
tDH
15.2
CE Controlled
OE tOES tOEH
ADDRESS tAS WE tCS CE tWPH tWP tDS DATA IN tDH tAH tCH
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16. Program Cycle Characteristics
Symbol tWC tAS tAH tDS tDH tWP tBLC tWPH Parameter Write Cycle Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High 100 0 50 35 0 90 150 Min Max 10 Units ms ns ns ns ns ns s ns
17. Program Cycle Waveforms(1)(2)(3)
Notes:
1. A7 through A15 must specify the sector address during each high-to-low transition of WE (or CE). 2. OE must be high when WE and CE are both low. 3. All bytes that are not loaded within the sector being programmed will be indeterminate.
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18. Software Data Protection Enable Algorithm(1)
LOAD DATA AA TO ADDRESS 5555
19. Software Data Protection Disable Algorithm(1)
LOAD DATA AA TO ADDRESS 5555
LOAD DATA 55 TO ADDRESS 2AAA
LOAD DATA 55 TO ADDRESS 2AAA
LOAD DATA A0 TO ADDRESS 5555
WRITES ENABLED
LOAD DATA 80 TO ADDRESS 5555
LOAD DATA TO PAGE (128 BYTES)(4)
ENTER DATA PROTECT STATE(2)
LOAD DATA AA TO ADDRESS 5555
LOAD DATA 55 TO ADDRESS 2AAA
Notes:
1. Data Format: I/O7 - I/O0 (Hex);Address Format: A14 - A0 (Hex). 2. Data Protect state will be activated at end of program cycle. 3. Data Protect state will be deactivated at end of program period. 4. 128 bytes of data MUST BE loaded.
LOAD DATA 20 TO ADDRESS 5555
EXIT DATA PROTECT STATE(3)
LOAD DATA TO PAGE (128 BYTES)(4)
20. Software Protected Program Cycle Waveform(1)(2)(3)
OE CE tWP WE A0-A6
5555 2AAA 5555 SECTOR ADDRESS
(1)
tWPH
tBLC
tAS
tAH
tDH
BYTE ADDRESS
A7-A15 DATA
(3)
(2)
tDS
AA 55 A0 BYTE 0 BYTE 126 BYTE 127
tWC
Notes:
1. A7 through A15 must specify the page address during each high-to-low transition of WE (or CE) after the software code has been entered. 2. OE must be high when WE and CE are both low. 3. All bytes that are not loaded within the sector being programmed will be indeterminate.
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21. Data Polling Characteristics(1)
Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay
(2)
Min 10 10
Typ
Max
Units ns ns ns
Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics.
0
ns
22. Data Polling Waveforms
23. Toggle Bit Characteristics(1)
Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay(2) OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. 150 0 Min 10 10 Typ Max Units ns ns ns ns ns
24. Toggle Bit Waveforms(1)(2)(3)
WE CE tOEH OE I/O6
(2)
tDH tOE
HIGH Z
tWR
Notes:
1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary.
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25. Software Product Identification Entry(1)
LOAD DATA AA TO ADDRESS 5555
LOAD DATA 55 TO ADDRESS 2AAA
LOAD DATA 90 TO ADDRESS 5555
PAUSE 10 mS
ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5)
26. Software Product Identification Exit(1)
LOAD DATA AA TO ADDRESS 5555
LOAD DATA 55 TO ADDRESS 2AAA
LOAD DATA F0 TO ADDRESS 5555
PAUSE 10 mS
EXIT PRODUCT IDENTIFICATION MODE(4)
Notes:
1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. A1 - A15 = VIL. Manufacturer Code is read for A0 = VIL; Device Code is read for A0 = VIH. 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code is 1F. The Device Code is 5D.
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27. Normalized ICC Graphs
NORMALIZED SUPPLY CURRENT vs. TEMPERATURE 1.4 N O R M A L I Z E D 1.3 1.2 1.1 1.0
I 0.9 C C 0.8 -55
-25
5
35
65
95
125
TEMPERATURE (C)
NORMALIZED SUPPLY CURRENT vs. ADDRESS FREQUENCY 1.1 N O R M 1.0 A L I 0.9 Z E D I C C 0.8
VCC = 5V T = 25C
0.7
0
1
2
3
4
5
6
7
FREQUENCY (MHz)
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 N O R M 1.2 A L I 1.0 Z E D I C C 0.8
0.6 4.50
4.75
5.00 SUPPLY VOLTAGE (V)
5.25
5.50
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28. Ordering Information
28.1
tACC (ns)
Standard Package
ICC (mA) Active 50 Standby 0.1 0.3 0.1 0.3 0.1 0.3 0.1 0.3 Ordering Code AT29C512-70JC AT29C512-70TC AT29C512-70JI AT29C512-70TI AT29C512-90JC AT29C512-90TC AT29C512-90JI AT29C512-90TI AT29C512-12JC AT29C512-12TC AT29C512-12JI AT29C512-12TI AT29C512-15JC AT29C512-15TC AT29C512-15JI AT29C512-15TI Package 32J 32T 32J 32T 32J 32T 32J 32T 32J 32T 32J 32T 32J 32T 32J 32T Operation Range Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C)
70 50 50 90 50 50 120 50 50 150 50
Note:
Not recommended for New Designs.
28.2
tACC (ns) 70 90
Green Package Option (Pb/Halide-free)
ICC (mA) Active 50 50 Standby 03 0.3 Ordering Code AT29C512-70JU AT29C512-70TU AT29C512-90JU AT29C512-90TU Package 32J 32T 32J 32T Operation Range Industrial (-40 to 85C) Industrial (-40 to 85C)
Package Type 32J 32T 32-lead, Plastic J-leaded Chip Carrier (PLCC) 32-lead, Thin Small Outline Package (TSOP)
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29. Packaging Information
29.1 32J - PLCC
1.14(0.045) X 45
PIN NO. 1 IDENTIFIER
1.14(0.045) X 45 0.318(0.0125) 0.191(0.0075)
E1 B
E
B1
E2
e D1 D A A2 A1
0.51(0.020)MAX 45 MAX (3X)
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL
D2
MIN 3.175 1.524 0.381 12.319 11.354 9.906 14.859 13.894 12.471 0.660 0.330
NOM - - - - - - - - - - - 1.270 TYP
MAX 3.556 2.413 - 12.573 11.506 10.922 15.113 14.046 13.487 0.813 0.533
NOTE
A A1 A2 D D1 D2
Note 2
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum.
E E1 E2 B B1 e
Note 2
10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 32J REV. B
R
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29.2 32T - TSOP
PIN 1
0 ~ 8
c
Pin 1 Identifier D1 D
L
e
b
L1
E
A2
A
SEATING PLANE
GAGE PLANE
A1
SYMBOL A A1 A2 Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. D D1 E L L1 b c e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.05 0.95 19.80 18.30 7.90 0.50 NOM - - 1.00 20.00 18.40 8.00 0.60 0.25 BASIC 0.17 0.10 0.22 - 0.50 BASIC 0.27 0.21 MAX 1.20 0.15 1.05 20.20 18.50 8.10 0.70 Note 2 Note 2 NOTE
10/18/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. 32T REV. B
R
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0456H-FLASH-2/05

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